Conventional technologies still have technical difficulties in dealing with the electrostatic discharge (ESD) problems in designing, manufacturing and implementing the semiconductor power devices. Specially, the high voltage transient signal from static discharge in a DMOS device can impose a voltage bias higher than 10,000 volts. The high electric field induced by the bias voltage when imposed on a relatively thin layer of gate dielectric layer often leads to hazardous conditions to the DMOS device. The thin layer of gate dielectric is most commonly implemented as an oxide layer. Under a high electric field, rupture is induced in the oxide layer that functions as an insulator. A permanent damage is thus introduced into a system implemented with the power semiconductor device. The reliability of system performance and operations suffer due this ESD problem. This problem is particularly pronounced in high voltage DMOS devices. Many ESD protective measures are implemented. DMOS devices are often designed and manufactured with self-contained ESD protection systems comprising multiple back to back Zener diodes as shown in FIG. 1. The ESD protection circuits can be implemented either as a discrete circuit or as an integrated part of the semiconductor power devices.
FIG. 1 shows the circuit equivalent for a typical N-channel DMOS in which a back to back Zener diode as ESD (Electrostatic Discharge) protection diode is located between the source and gate of the DMOS. The ESD protection diode breaks down when the gate to source voltage exceeds a specified voltage value.
FIG. 2 and FIG. 3 illustrate an example of a conventional trench DMOS structure having ESD protection and its disadvantage.
Refer to FIG. 2, which is about U.S. Pat. No. 6,657,256 and No. 6,884,683, the structure includes an n+ substrate 200 on which is grown a lightly n-doped epitaxial layer 204. Within doped epitaxial layer 204, a body region 216 of opposite conductivity is provided. An n-doped layer 240 that overlies most of the body region 216 serves as the source. A rectangularly shaped trench 224 is provided in the epitaxial layers. A gate oxide layer 230 lines the sidewalls of the trench 224. The trench 224 is filled with polysilicon 252. An ESD protection poly diode is two back to back Zener diode comprising two n+ regions 245 and one P region 248. A thin layer of oxide is formed underneath the ESD protection diode acting as the insulating layer, as shown in FIG. 2.
FIG. 3 shows the disadvantage of the DMOS structure of FIG. 2 when trenched contacts into the epitaxial layer and the ESD diode are applied. The ESD protection diode is shorted with body-source region as a result of the doped poly over-etching region 260, and the insulator etch-through caused by poor etching selectivity of the oxide over the doped poly.
One problem with the device shown in the previously mentioned patent is that when trench contacts are applied for source and gate, it requires additional Si trench etch procedure as shown on FIG. 2. Such arrangement will encounter the problem including the ESD diode shorting with body-source and therefore result in low yield and product reliability as shown on FIG. 3. The shortage is resulted from etch through ESD diode poly and thin oxide underneath mentioned above, which will result in permanent damage to the device.
There is a need in the art for a system and method for providing overvoltage protection to prevent the ESD shortage problems in connection in the design of trench DMOS transistor.